The invention relates to the fabrication of integrated circuit devices, and more particularly, to a semiconductor device having reduced junction capacitance by an additional low dose super deep source/drain implant, and to a method for fabricating such a device.
As the semiconductor industry progresses to even smaller sub-micron dimensions, continued advances in manufacturing techniques are required to provide submicron semiconductor devices with acceptable electrical characteristics. As CMOS gate lengths are reduced, the risk of a short-channel effect, called punch-through, rises. Punch-through is a circuit breakdown in which the drain voltage reaches a sufficiently large value that the depletion layer associated with the drain spreads across the substrate and reaches the source. This causes a destructive source/drain conduction path or leakage current.
Various approaches have been taken to avoid short-channel effects. One technique for avoiding punch-through is to raise the well or substrate dopant concentration, reducing the size of the depletion region so that punch-through does not occur when a voltage is applied. However, increasing the well concentration has drawbacks. The high substrate doping level causes a high source/drain junction capacitance, a low junction breakdown voltage, an increase in transistor threshold voltage, and high body effects. Furthermore, a high well concentration reduces carrier mobility, leading to a lowering of drive current.
Anti-punchthrough (APT) implants have been developed as an alternative to raising the dopant concentration generally throughout the well or substrate. APT implants increase dopant concentrations only near the channel and source/drain region, not throughout the entire substrate. Examples of such APT implants are halo implants and pocket implants, which are illustrated by FIG. 1.
Over a semiconductor substrate 10, a polycide gate 11 is formed. Heavily doped source and drain (HDD) regions 24 and lightly doped source and drain (LDD) regions 30 have been implanted. On a respective side of the polycide gate 11, for convenience of illustration, there is either a halo implant 17 or a pocket implant 34. The halo implant 17 is a self-aligned implant in which the polycide gate 11 acts as a mask during implant. The halo implant 17 is performed with a dopant opposite to that of the implant in the LDD regions 30. As illustrated, the halo implant 17 is deeper both vertically and laterally than its respective LDD region 30.
The pocket implant 34 is also a self-aligned implant in which a small pocket of a heavy dopant concentration is formed adjacent the LDD regions 30 to block the potential leakage path while allowing the channel region 15 to maintain a lower dopant concentration. In particular, the pocket implant 34 raises dopant concentrations only where the increased doping is needed, rather than raising the well concentration uniformly throughout the substrate 10, as is the case with the halo implant 17.
However, providing a pocket implant under the LDD regions by conventionally known methods, such as disclosed by U.S. Pat. No. 5,595,919, is both complicated and expensive by requiring additional processing steps, which adds production cost to the integrated circuit device. Accordingly, the present inventors have recognized a need for further improvements in semiconductor processing to provide reduce junction capacitance in the fabrication of integrated circuits by less complicated methods, requiring fewer processing steps, thereby reducing production costs.